From ff7bf97203fd5b24d4b14626c931b37933f3ddf6 Mon Sep 17 00:00:00 2001
From: Eugene Cohen <quic_egmc@quicinc.com>
Date: Tue, 20 Jan 2026 10:17:28 -0800
Subject: [PATCH] add rv32imac_mp to support PMP

---
 src/sysc/register_cores.cpp | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/sysc/register_cores.cpp b/src/sysc/register_cores.cpp
index 6e02119..9b49053 100644
--- a/src/sysc/register_cores.cpp
+++ b/src/sysc/register_cores.cpp
@@ -40,6 +40,7 @@
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/arch/riscv_hart_msu_vp.h>
+#include <iss/mem/pmp.h>
 #include "iss_factory.h"
 #include "core2sc_adapter.h"
 #include <array>
@@ -48,7 +49,8 @@
 namespace iss {
 namespace interp {
 using namespace sysc;
-volatile std::array<bool, 14> riscv_init = {
+__attribute__((used))
+volatile std::array<bool, 15> riscv_init = {
     iss_factory::instance().register_creator("rv32i_m:interp",
                                              [](unsigned gdb_port, sysc::riscv::core_complex_if* cc) -> iss_factory::base_t {
                                                  auto* cpu = new core2sc_adapter<arch::riscv_hart_m_p<arch::rv32i>>(cc);
@@ -64,6 +66,12 @@ volatile std::array<bool, 14> riscv_init = {
                                                  auto* cpu = new core2sc_adapter<arch::riscv_hart_m_p<arch::rv32imac>>(cc);
                                                  return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast<arch::rv32imac*>(cpu), gdb_port)}};
                                              }),
+    iss_factory::instance().register_creator("rv32imac_mp:interp", // rv32imac_m with PMP
+                                             [](unsigned gdb_port, sysc::riscv::core_complex_if* cc) -> iss_factory::base_t {
+                                                 auto* cpu = new core2sc_adapter<arch::riscv_hart_m_p<arch::rv32imac>>(cc);
+                                                 cpu->memories.insert_before_last(std::make_unique<iss::mem::pmp<iss::arch::rv32imac>>(cpu->get_priv_if()));
+                                                 return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast<arch::rv32imac*>(cpu), gdb_port)}};
+                                             }),
     iss_factory::instance().register_creator("rv32imac_mu:interp",
                                              [](unsigned gdb_port, sysc::riscv::core_complex_if* cc) -> iss_factory::base_t {
                                                  auto* cpu = new core2sc_adapter<arch::riscv_hart_mu_p<arch::rv32imac>>(cc);